1. Field of the Invention
This invention relates to voltage comparators, and more particularly to designing fast comparators that can accurately compare signals to ground level.
2. Description of the Related Art
Comparators are devices that typically compare two voltages or two currents, switching their respective outputs to indicate which of the two input signals is larger. Oftentimes comparators are analog circuits used in a variety of applications. One implementation of comparators may be directed towards detecting the level of an input signal relative to a zero-level voltage, or ground, in switching power regulators operating in a PFM (pulse-frequency-modulation) mode. Many different types of comparators exist, each with different advantages and disadvantages. Open loop, uncompensated two-stage operational amplifier (op-amp) based comparators implemented with PMOS (P-channel Metal Oxide Semiconductor) input devices are capable of sensing ground level, typically have a high gain, but may be rather slow when consuming low power.[1] Generally, PMOS input, cross-coupled comparators have a high offset and feature a low gain, but are not suitable for sensing near zero-level (ground) voltages. [1] Philip Allen, “CMOS Analog Circuit Design”, chapter 7. Oxford, 1987
One type of comparator that may typically be used for sensing ground within a switching power regulator features a PMOS input, gain-enhanced current-mirror configuration. One example of such a comparator (100) is shown in FIG. 1. Comparator 100 is implemented with source-coupled differential input pair PMOS devices 102 and 104 receiving current from current source 128, with positive feedback to provide a high gain and increase response time. Surprisingly, comparator 100 shows a relatively low gain in simulation. When configured to sense ground (or zero voltage), input Vin− 122 may be coupled to a zero volt (ground) reference. If Vin+ 124 is below ground level, for example at −10 mV, and VGS[102] (the gate-source voltage of PMOS device 102) is at 1V, then because of Vin− 122 residing at a zero volt level, the voltage at node A would be at 1V, with VDS[102] (the drain-source voltage of PMOS device 102) following the voltage at node A. In general, PMOS devices 102 and 104 would not be in saturation, resulting in a very low DC gain of the first stage. A low DC gain would in turn lead to comparator 100 having a high offset and operating with low efficiency.
Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.